Many advancements have been made in the field of power integrated circuits in the development of power transistors. Lateral double diffused metal oxide semiconductor transistors (LDMOS) have been the power devices of choice for integration into very large scale integrated circuit logic processes. The on-resistance per unit area (r.sub.ds (on)) is a figure of merit for a high voltage power device. LDMOS power transistors exhibit low on-resistance and high breakdown capability concurrently through a reduced surface field (RESURF technique) introduced by J. A. Apples and H. M. J. Vaesn "High Voltage Thin Layer Devices" (RESURF devices), IEDM Tech. Digest, pp. 238-241, 1979.
In integrated circuit design, semiconductor die area is a crucial factor. Generally, an increase in transistor area results in a decrease in on-resistance of the transistor. Therefore, a crucial design constraint is the trade off between transistor performance and device cost. This trade off problem has driven research into new transistor structures that provide low on-resistance while simultaneously minimizing transistor area. One proposed improvement has been the development of a trench DMOS transistor by Ueda, et al. in "An Ultra-Low On-Resistance Power MOSFET Fabricated by Using a Fully Self Aligned Process", IEEE Transactions on Electron Devices, Vol. ED-34, No. 4, April 1987. However, further improvements can be made to the trench DMOS transistor in order to obtain a low on-resistance and a high blocking voltage.
From the foregoing, it may be appreciated that a need has arisen for a DMOS transistor having a low on-resistance and a high blocking voltage using a trench structure.